1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a multibank, that is, a plurality of banks divided from a single large memory cell array.
2. Description of the Related Art
As the power of microprocessors continues to increase, the access time to memory must continue to decrease so that the utility of these powerful microprocessors is realized. Additionally, since more data needs to be available to the newer powerful microprocessors, the size of memory storage units will detrimentally increase if steps are not taken to reduce their size requirements as well as access speed. Furthermore, the reduction of power consumption by a memory device is an on-going challenge in the development of new memory devices.
More particularly, in a system using general semiconductor memory device hierarchy, the bandwidth of the semiconductor memory devices, especially DRAMs, is small. Therefore, bank interleaving is generally used to transmit a large amount of data within a predetermined time. In bank interleaving, several memory devices are each divided into a plurality of banks and a memory controller successively obtains data from each bank. That is, interleaving provides the simultaneous accessing of two or more bytes or streams of data from distinct storage units. Disk drives for example, normally interleave sectors on the storage media so that they can read successive sectors in one pass of the read/write heads. Without this, i.e. if the sectors were arranged in sequence physically, the drive might not have enough time to read successive sectors and consequently access time would be longer. Recently, the interleaving function has been performed with a single semiconductor memory device by providing a plurality of banks to the semiconductor device.
FIG. 1 is a schematic block diagram of a conventional semiconductor memory device having a multibank including a plurality of cell arrays all part of a single bank. Here, a single bank A and portions related to column decoding are shown.
Referring to FIG. 1, in the conventional semiconductor memory device having a multibank, a bank, for example, bank A includes a single independent large memory cell array 1, a column decoder 5, and a row decoder 7. The large memory cell array 1 includes a plurality of unit memory cell arrays 2, and is shown to have sixteen unit memory cell arrays 2 in FIG. 1. The output ports of the column decoder 5 are connected to a plurality of column selection lines CLS0(A).about.CSLn(A) all of which are part of a single bank A. The output ports of the column decoder 5 are further connected to a plurality of column selection lines CLS0 (A)-CLSn(A). The single bank column decoder 5 enables column selection lines CLS0(A).about.CLSn(A) in pairs, in response to a plurality of first predecoding signals PDCA23, PDCA45, and PDCA67, a second predecoding signal DCA01, and a reset pulse CSLRSP. That is, the column selection lines CSL0(A).about.CSLn(A) are enabled in pairs by the same column address, and select a column corresponding to the single bank A. In addition, each of the column selection lines CSL0(A).about.CSLn(A) are connected to four switching transistors 3 at both sides of the unit memory cell arrays 2. The connection between the column selection lines and the switching transistors will be described in detail referring to FIG. 2.
In addition, the conventional semiconductor memory device having a single multibank includes first and second column predecoders 13 and 15, a bank selection bit buffer 17, a column address buffer 19, first and second delays 21 and 23, and a clock buffer 25. The column address buffer 19 buffers externally input column address bits A0.about.A7, and the bank selection bit buffer 17 buffers externally input bank selection bits BS0 and BS1. The first column predecoder 13 decodes outputs PBS0 and PBS1 of the bank selection bit buffer 17 and CA2.about.CA7 which are some of the outputs of the column address buffer 19, and generates the plurality of first predecoding signals PDCA23, PDCA45, and PDCA67. The second column predecoder 15 decodes CA0 and CA1 which are others of the outputs of the column address buffer 19, in response to an internal delayed clock signal PCLKD, and generates the second predecoding signal DCA01. The clock buffer 25 buffers an externally input clock signal CLK and outputs an internal clock signal PCLK. The first and second delays 21 and 23 delay the internal clock signal PCLK, respectively, and generate the delayed clock signal PCLKD and the reset pulse CSLRSP.
FIG. 2 is a circuit diagram showing the connections between the column selection lines and the switching transistors in the conventional semiconductor memory device having a single multibank.
Referring to FIG. 2, one of the two same column selection lines CLSi(A) enabled by the same column address is connected to each gate of four switching transistors S1, S2, S3, and S4 which connect four of input and output lines I/O to two pairs of bit lines and complementary bit lines BLi, BLi, BLi+1, and BLi+1 in the conventional semiconductor memory device having a multibank. The other column selection line is connected to each gate of four switching transistors S5, S6, S7, and S8 which connect the other four of input and output lines I/O to two pairs of bit lines and complementary bit lines BLi+2, BLi+2, BLi+3, and BLi+3. Sense amplifiers SA1, SA2, SA3, and SA4 are connected between the bit lines and the complementary bit lines which are given in pairs.
Isolation gates T.sub.i1 -T.sub.i8 are connected respectively between the bit lines and complementary bit lines of unit memory cell arrays at the left side, including memory cells ML, and the sense amplifiers SA1, SA2, SA3, and SA4. Isolation gates T.sub.j1 -T.sub.j8 are connected between the bit lines and complementary bit lines of unit memory cell arrays at the right side, including memory cells MR, and the sense amplifiers SA1, SA2, SA3, and SA4.
In the conventional semiconductor memory device having a multibank as described above, when the single large memory cell array 1 is divided into a plurality of banks, for example, two banks, (i.e. banks A and B), it is necessary to use the column selection lines CSL0(A).about.SLn(A) together in both banks. Thus, when the rows of both banks are activated by the row decoder 7 and data of a memory cell is read by selecting the column of either bank, the same column selection line is used in the other non-selected bank, in the conventional semiconductor memory device. Therefore, current flows from a power voltage VCC to a ground voltage VSS through load transistors of the input and output lines I/O, the switching transistors connecting the input and output lines I/O to the bit lines and complementary bit lines, and the N-type sense amplifiers. Accordingly, in the case that the large memory cell array 1 is divided into two banks in the conventional semiconductor memory device having a multibank, power consumption detrimentally increases when the data of a memory cell is read. Therefore, when a large memory cell array is divided into a plurality of banks, each bank should have its own column decoder to prevent such increased power consumption. However, with this solution, chip size detrimentally increases.